1. Field of the Invention
The present invention relates generally to the conversion of an input sequence of randomly arriving codes of first or second type or a mixture thereof into an output sequence of predetermined format, and more specifically to conversion of a series of eight decoded 8B/10B codes (i.e., 64B) to a 65B block and inverse conversion of the 65B block to a sequence of eight eight-bit codes.
2. Description of the Related Art
According to the GFP (Generic framing Procedure) draft standard currently under study by the ANSI T1X1.5, frames such as Ethernet and PPP protocol are encapsulated in a frame of higher or lower layer for transmission over SONET/SDH transport networks. The GFP standard also defines a format for encapsulating stream data of 8B/10B block codes into a frame. The 8B/10B block code is extensively used in a number of protocols such as Gigabit Ether, fiber channels and DVD-ASI standard. When encapsulating a 8B/10B code in a GFP frame, eight 8B/10B codes are converted to a data block of 65 bits and this conversion process is known as a 64B/65B conversion.
However, the computation involved in the current 64B/65B conversion process and 65B/64B conversion process (inverse conversion of 64B/65B conversion) are considerably complex and requires a substantial amount of hardware.
It is therefore an object of the present invention to provide a code converter and a method of code conversion that eliminate redundant computations involved with the prior art conversion processes by utilizing the inherent property of the protocol, i.e., code sequence integrity.
According to a first aspect of the present invention, there is provided a code converter for receiving a sequence of randomly arriving input codes of first and second types, comprising storage circuitry for storing the input codes of the first type in first sequential positions in order of arrival, storing the input codes of the second type in second sequential positions in order of arrival, and storing order-of-arrival indications of the input codes in third sequential positions, and control circuitry connected to the storage circuitry for organizing contents of the first, second and third sequential positions into a predetermined format according to a signal indicating whether the input code is of the first type or the second type, the organized format containing an identification code indicating whether or not the organized format is a mixture of the first and second types of input codes. Preferably, the control circuitry comprises a first counter for producing a first count value indicating a count number of input codes of the first type, and a second counter for sequentially producing a second count value indicating an order of arrival of each of the input codes in the sequence of random arrival. The formatting circuitry organizes contents of the first, second and third sequential positions into the predetermined format according to the first count value when the second count value attains a predetermined value.
According to a second aspect, the present invention provides an inverse code converter for receiving a sequence of input codes of first and second types, the input codes of the firs type being consecutively arranged in the sequence and the input codes of the second type being consecutively arranged in the sequence, the sequence containing an identification code indicating whether or not the sequence Is a mixture of the first and second types of input codes and position indications of the input codes of the first type in the sequence. The inverse converter comprises first detector circuitry for detecting the input codes of the first type according to the identification code and producing a count number of the input codes of the first type, first reordering circuitry for reordering the input codes of the first type according to the position indications and the count number, second detector circuitry for producing a type-indication signal indicating whether each of the input codes is of the first type or the second type based on the position indications and the count number, position detector circuitry for determining the position of each input code of the second type in an output sequence according to the type-indication signal, second reordering circuitry for reordering each of the input codes of the second type according to the position determined by the position detector circuitry, and selector circuitry for selecting one of the reordered input code of the first type and the reordered input code of the second type according to the type-indication signal.